1. Field of the Invention
The present invention relates to an effective address cache memory, a processor and an effective address caching method, and more particularly to an effective address cache memory, a processor and an effective address caching method for a processor configured to support an effective storage.
2. Description of the Related Art
Conventionally, in a processor configured to employ an effective storage, in order to execute address translation at high speed from an effective address space which is an address space unique to a process, to a real address space which is an address space of an entire computer system in which the processor is mounted, a TLB (Translation Lookaside Buffer) which is a dedicated cache memory configured to place a copy of a page table managed by an operating system (hereinafter, referred to as “OS”) is mounted.
On the other hand, in order to hide latency of memory accesses, the processor copies data in a memory to a cache memory (hereinafter, also referred to as “cache”) and uses the data. In order to specify an address of the data in the memory which retains the data copied to the cache, the processor has a Tag memory configured to retain the address of the data and a status of the data (whether or not the data is valid, whether or not memory contents have been updated, or the like), in addition to a data memory configured to retain the data in the memory. The tag memory is generally configured to set low-order bits of a memory address as an index of the cache, and to retain high-order bits (Tag) of the memory address and the status of the data, as data.
The above described address translation often becomes a critical path in terms of timing in processor design. If the processor employs a hierarchical memory, a configuration may often be employed in which a level 1 cache (hereinafter, also referred to as “L1 cache”) positioned near the processor is accessed by using an effective address, and level 2 (L2 cache) and more caches are accessed by using a real address because of measures against an alias to be described later or the like.
Since the address translation is performed in all the memory accesses caused by fetch of instructions, a load instruction and a store instruction, performance is more affected by a TLB miss than by a normal cache miss. Thus, the TLB is provided as the dedicated memory separated from the cache.
However, the above described conventional configuration of the TLB and the cache memory has the following problem.
The problem relates to capacities of the TLB, and the tag memory of the cache.
The TLB retains data such as an effective page number, a real page number, a page attribute and a page status, as the data. In a processor having a real address space of 32 bits or more, the effective page number and the real page number have a high proportion of the data retained in the TLB. A size of the TLB mainly depends on a size of the real address space, a minimum page size, and the number of entries in the TLB.
The tag memory of the cache retains data such as the Tag and a cache status, as the data. In the processor having the real address space of 32 bits or more, the Tag has a high proportion of the data retained in the tag memory of the cache. A size of the tag memory of the cache mainly depends on the size of the real address space, a cache line size and a cache capacity.
According to “Computer Architecture—A Quantitative Approach—Third Edition”, Figures 5.57 and 5.58 (pages 505 and 506), recent processors are as follows.                A L1 size is 8 kB to 64 kB, direct mapped or 2-way set associative.        The number of TLB entries is 4 to 512 entries, full associative.        The minimum page size is 1 to 64 kB.        
Moreover, a basic technique of a cache using an effective address is also disclosed in “Computer Organization and Design—The Hardware/Software interface—second edition” (1998 Morgan Kaufmann: ISBN 1-55860-428-6) by David. A. Patterson and John L. Hennessy (p 592) Integrating virtual memory, TLB and Caches (p 593) Figure 7.25 (p 594) Figure 7.26, and “Computer Architecture—A Quantitative Approach—third edition” (2003 Morgan Kaufmann: ISBN 1-55860-596-7) by John L. Hennessy and David. A. Patterson (p 444) “Second Hit Time Reduction Technique: Avoiding Address Translation during Indexing of Cache”.